Thin Film Delamination (TFD) is a plastic package specific failure mechanism. When a thin film stack such as a semiconductor device is packaged, the thin film stack is exposed to moisture stress. Specifically, a moisture sensitive film reacts with moisture coming, for example, from the die edge. Adhesion of this moisture sensitive film weakens and delamination occurs when the film stack is under shear stress.
FIG. 1 illustrates thin film delamination. In FIG. 1, a semiconductor structure 10 comprises a substrate 12 and a plurality of thin films 14 stacked thereon. Illustratively, the substrate 12 is silicon, and the thin films 14 may be oxide layers, dielectric layers, metallization, poly, glass layers such as BPSG layers, etc. A shear stress 16 results in the delamination 20, wherein there is a separation along the boundary between two of the layers.
It is especially desirable to be able to test a semiconductor device fabrication and packaging process for Thin Film Delamination failure mechanisms. To perform such testing, one or more thin film delamination test chips are incorporated into a processed semiconductor Wafer. The wafer is then sawed into a plurality of die sizes. The dice are assembled in different plastic packages depending on die size and subjected to environmental stress. Each die has a delamination test chip which indicates whether or not there is delamination in that die.
A prior art delamination test chip for detecting thin film delamination is disclosed in Hong "Thin Film Cracking/Delamination Evaluation Using Assembly Test Chip." The prior art delamination test chip is illustrated in FIG. 2.
The delamination test chip 20 of FIG. 2, comprises a substrate 22 and a plurality of thin films. The thin films are labeled thin film #1, thin film #2, thin film #3, thin film #4, thin film #5, thin film #6, and thin film #7. Illustratively, each film corresponds to a film or layer in a semiconductor device formed on the same die as the delamination test chip. The test chip 20 comprises a "via/metal/poly chain" running up and down the stack of thin films.
Specifically, thin films #1, #3, #5, and #7 include polysilicon films 26 and the thin films #2, #4, and #6 include vias 28 which connect the polysilicon films 26. For example, each of the vias 26 in the film #2 connect the polysilicon film in the film #1 with one of the two polysilicon films in the film #3.
The delamination test structure 20 of FIG. 2 operates as follows. When there is no delamination there is a short between the two conducting layers in film #7 which function as probing contacts, because the "via/metal/poly" chain provides a conducting path between these conducting layers. However, when delamination occurs the via/contact chain is disturbed and there is a change in resistance between the two conducting layers in film #7.
A shortcoming of the delamination test chip shown in FIG. 2 is that it cannot be used to identify at which layer the delamination occurs. It is an object of the present invention to overcome this shortcoming by providing a delamination test chip which identifies at which layer in a thin film structure delamination occurs.